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  ? semiconductor components industries, llc, 2001 november, 2001 rev. 0 1 publication order number: and8075/d and8075/d board mounting considerations for fcbga packages prepared by: phill celaya, packaging manager mark d. barrera, broadband knowledge engineer application note usage this application note provides an overview of some of the unique considerations related to the mounting of bga packages on a pcb. the sited references include information on pcb layout for systems engineers, and manufacturing processes for manufacturing process engineers. introduction bga (ball grid array) packages are often the package of choice for optimizing device electrical performance. they are lightweight, thin, and minimize the use of board space. to take advantage of bga packaging, special preparations and guidelines have to be followed to ensure the proper mounting of the device onto the pcb. this document outlines many of the processes and board design considerations for mounting bga devices. bga package overview package interconnects there are many bga package types, but the die for all types is connected to the package substrate by the wirebond method (figure 1), or by the flipchip direct attachment method (figure 2). the csp, pbga, and fcbga are the most common bga package types. a chip scale package (csp) can have either wirebond or flipchip die interconnects. a typical plastic ball grid array (pbga) has wirebond interconnects. a typical flipchip ball grid array (fcbga) has flipchip interconnects. once the die is connected to the substrate, the package is overmolded with a plastic molding compound. figure 1. crosssection of wirebond pbga resin seal package board (organic) solder ball eutectic solder balls mold compound glass epoxy substrate flip chip device figure 2. crosssection of fcbga package ball grid arrays the xy solder ball grid array on the underside of the package is used to connect to the pcb substrate. the grid spacings have been standardized under jedec guidelines. the most commonly used grid spacings are 0.8, 1.0, and 1.27 mm. http://onsemi.com application note
and8075/d http://onsemi.com 2 printed circuit board (pcb) design smd and nsmd pad configurations the solder masked defined (smd) and nonsolder masked defined (nsmd) pad configurations are commonly used for surface mount bga packages. the pad configurations are shown below in figure 3. figure 3. smd and nsmd pad configurations solder mask defined (smd) pad non solder mask defined (nsmd) pad b a b a a b a b b a with smd configured pads, the solder mask covers the outside perimeter of the circular contact pads. with this configuration, the solder flows over the top surface of the contact pad, and is prevented from flowing along the sides of the pad by the solder mask. with nsmd configured pads, there is a gap between the solder mask and the circular contact pad (refer to figure 3). with this configuration, the solder flows over the top surface and the sides of the contact pad. the additional nsmd soldering area results in a stronger mechanical bond. in addition, the additional area allows nsmd pads to be smaller than smd pads. the smaller size is beneficial for system designers as they allow more room for escape trace routing. smd design dimensions on semiconductor recommends that the solder mask opening size equal the package ball size if package escape trace routing is not a constraint. refer to table 1 for the optimal smd design dimensions. dim refers to the dimensions given in figure 3. table 1. optimal smd design dimensions (mm) dim smd dimension 0.80 mm ball pitch 1.00 mm ball pitch package ball size 0.40 0.50 0.40 0.50 a solder pad diameter 0.55 0.55 0.55 0.65 b solder mask opening 0.40 0.45 0.40 0.50 if package escape trace routing is a constraint, the solder mask opening size and the solder pad size may be decreased to 80% of the optimal sizes. refer to table 2 for the 80% of optimal smd design dimensions. dim refers to the dimensions given in figure 3. table 2. minimal smd design dimensions (mm) dim smd dimension 0.80 mm ball pitch 1.00 mm ball pitch package ball size 0.40 0.50 0.40 0.50 a solder pad diameter 0.44 0.44 0.44 0.52 b solder mask opening 0.32 0.36 0.32 0.40
and8075/d http://onsemi.com 3 nsmd design dimensions on semiconductor recommends that the pcb solder pad size equal the package ball size if package escape trace routing is not a constraint. refer to table 3 for the optimal nsmd design dimensions. dim refers to the dimensions given in figure 3. table 3. optimal nsmd design dimensions (mm) dim nsmd dimension 0.80 mm ball pitch 1.00 mm ball pitch package ball size 0.40 0.50 0.40 0.50 a solder pad diameter 0.40 0.45 0.40 0.50 b solder mask opening 0.55 0.55 0.55 0.65 if package escape trace routing is a constraint, the solder pad size and the solder mask opening size may be decreased to 80% of the package ball size. refer to table 4 for the 80% of optimal nsmd design dimensions. dim refers to the dimensions given in figure 3. table 4. minimal nsmd design dimensions (mm) dim nsmd dimension 0.80 mm ball pitch 1.00 mm ball pitch package ball size 0.40 0.50 0.40 0.50 a solder pad diameter 0.32 0.36 0.32 0.40 b solder mask opening 0.44 0.44 0.44 0.52 trace tapering dimensions pcb surface traces often vary in width over their length due to impedance and routing considerations. trace tapering dimensions must meet certain design rules or incorrect solder flow may result. trace tapering dimensions are described below in figure 4 illustrated with an nsmd pad design. figure 4. trace taper dimensions c d table 5 lists the trace tapering dimensions for printed circuit boards with smd or nsmd configured pads. dimensions c and d refer to figure 4. dimension c is derived from the design rule that the entering trace width must equal or be less than onehalf of the pad diameter. dimension d is derived from the design rule that if a wide trace is too close to the solder pad, the trace will pull solder away from the solder pad during reflow. ball collapse dimensions solder ball collapse dimensions are predictable if a defined solder paste reflow process is in place. a cross section of the assembled bga package on the pcb is described below in figure 5. figure 5. ball collapse dimensions pcb overall height <1.3 mm max. 0.2 mm typical (not to scale) table 5. trace tapering dimensions (mm) dim description 0.80 mm ball pitch 1.00 mm ball pitch package ball size 0.40 0.50 0.40 0.50 c maximum trace width 0.15 0.18 0.15 0.20 d minimum trace length 0.15 0.15 0.15 0.15
and8075/d http://onsemi.com 4 escape trace routing a variety of escape trace routing methods may be used including tapering and the use of escape vias. figure 6 illustrates two techniques for routing from the package to the pcb. one technique uses a plated through hole (pth) to connect the innerpower and innersignal balls to the pcb. another technique uses escape traces to connect the outersignal balls to the pcb. signal integrity must be ensured when laying out the escape routing. this is especially critical for devices where highspeed rf signals have been routed to the innersignal balls. figure 6. escape trace routing smt process recommendations process flow the following processes must be defined and controlled in order to establish a smt process: 1. plating of the pcb i/o contacts to the package. 2. screening/stenciling the solder paste onto the pcb. 3. choosing the proper solder paste. 4. placing the package onto the pcb. 5. reflowing the solder paste. 6. final solder joint inspection. 7. rework process (if necessary). pcb i/o contacts plating there are two common plated solderable metallizations which are used for pcb surfaces mount devices. in both cases it is imperative that the plating is uniform, conforming, and free of impurities to insure a consistent solderable system. the first metallization consists of plating electroless nickel over the copper pad, and then plating again with immersion gold. the allowable stresses and the temperature excursions the board will be subjected to throughout its lifetime will determine the thickness of the electroless nickel layer. gold thickness is recommended to be 0.15  m +/ 0.05  m. having excessive gold in the solder joint can create gold embrittlement which may effect the reliability of the joint. the second recommended solderable metallization is the use of an organic solderability preservative coating (osp) over the copper plated pad. the organic coating assists in preserving the copper metallization for soldering. solder screening the solder is typically patterned onto the pcb by using a 0.127 to 0.152  m (0.005 to 0.006 in) thick screen. the screen is designed and manufactured to only allow a specific amount of solder to be placed on the contact pads. it is recommended that the side walls of the screen openings be tapered approximately 5 degrees to facilitate the release of the paste when the screen is removed from the pcb. solder paste type type 3 or 4 solder paste is recommended. package placement pick and place equipment with the standard tolerance of  0.10 mm or better is recommended. bga packages exhibit excellent selfalignment properties during solder reflow. the ball can be misaligned up to 50% and it will still selfalign.
and8075/d http://onsemi.com 5 solder paste reflow a standard surface mount reflow process can be used once the package and the solder paste are placed on the pcb. an example of a standard reflow profile is shown in figure 5. the exact recommended reflow profile is determined by the manufacturer of the paste since the chemistry and viscosity of the flux matrix will vary. these variations will require small changes in the profile in order to achieve an optimized process. in general, the temperature of the part should be raised less than or equal to 2 c/sec during the initial stages of the reflow profile. the soak zone then occurs when the part is approximately 150 c and should last for 30 to 120 seconds. the temperature is then raised and will be above the liquidus of the solder for 30 to 100 seconds depending on the mass of the board. the peak temperature of the profile should be between 205 and 225 c. figure 7. typical reflow profile for eutectic sn/pb solder 0 minutes degrees ( c) 0.7 1.3 2.0 2.7 3.3 4.0 4.7 0 100 200 300 solder joint inspection the inspection of solder joints is commonly performed with an xray inspection system. the xray system is used to locate open contacts, shorts between pads, solder voids, and extraneous solder. rework process bga packages use solder balls for pcb interconnects, therefore the entire package must be removed from the pcb if rework is required. it is important to minimize the chance of overheating neighboring packages during removal if the package is in close proximity to adjoining packages. standard smt rework systems are recommended for this procedure since the airflow and temperature gradients can be carefully controlled. a nitrogen atmosphere is typically used to prevent solder ball oxidation during rework. it is also recommended that the pc board be placed in an oven at 125 c for 12 hours prior to heating the parts to remove excess moisture from the packages. the package can be removed after the solder has been heated above its liquidus temperature. the pcb pads must then be thoroughly cleaned, and the solder paste dispensed. a new device can then be reflowed onto the board. references 1. ipc sm782a. surface mount design and land pattern standard. 2. ipc 7095. design and assembly process implementation for ball grid arrays. 3. jedec jstd013. implementation of ball grid array and other high density technologies.
and8075/d http://onsemi.com 6 notes
and8075/d http://onsemi.com 7 notes
and8075/d http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8075/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada


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